RELOAD_SEL=0, INIT_SEL=00, INDEP=0, CLK_SEL=00, FORCE_SEL=000, FRCEN=0
Control 2 Register
| CLK_SEL | Clock Source Select 0 (00): The IPBus clock is used as the clock for the local prescaler and counter. 1 (01): EXT_CLK is used as the clock for the local prescaler and counter. 2 (10): Submodule 0’s clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. |
| RELOAD_SEL | Reload Source Select 0 (0): The local RELOAD signal is used to reload registers. 1 (1): The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. |
| FORCE_SEL | This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 0 (000): The local force signal, CTRL2[FORCE], from this submodule is used to force updates. 1 (001): The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. 2 (010): The local reload signal from this submodule is used to force updates without regard to the state of LDOK. 3 (011): The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 4 (100): The local sync signal from this submodule is used to force updates. 5 (101): The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 6 (110): The external force signal, EXT_FORCE, from outside the PWM module causes updates. 7 (111): The external sync signal, EXT_SYNC, from outside the PWM module causes updates. |
| FORCE | Force Initialization |
| FRCEN | This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL] 0 (0): Initialization from a FORCE_OUT is disabled. 1 (1): Initialization from a FORCE_OUT is enabled. |
| INIT_SEL | Initialization Control Select 0 (00): Local sync (PWM_X) causes initialization. 1 (01): Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. 2 (10): Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. 3 (11): EXT_SYNC causes initialization. |
| PWMX_INIT | PWM_X Initial Value |
| PWM45_INIT | PWM45 Initial Value |
| PWM23_INIT | PWM23 Initial Value |
| INDEP | Independent or Complementary Pair Operation 0 (0): PWM_A and PWM_B form a complementary PWM pair. 1 (1): PWM_A and PWM_B outputs are independent PWMs. |
| WAITEN | WAIT Enable |
| DBGEN | Debug Enable |